NXP Semiconductors /LPC11Axx /SYSCON /SYSAHBCLKCTRL

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Interpret as SYSAHBCLKCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RESERVED)SYS 0 (DISABLE)ROM 0 (DISABLE)RAM 0 (DISABLED)FLASHREG 0 (DISABLED)FLASHARRAY 0 (DISABLE)I2C 0 (DISABLE)GPIO 0 (DISABLE)CT16B0 0 (DISABLE)CT16B1 0 (DISABLE)CT32B0 0 (DISABLE)CT32B1 0 (DISABLE)SSP0 0 (DISABLE)UART 0 (DISABLE)ADC 0RESERVED 0 (DISABLE)WDT 0 (DISABLE)IOCON 0RESERVED 0 (DISABLE)SSP1 0 (DISABLE)PINT 0 (DISABLE)ACOMP 0 (DISABLE)DAC 0RESERVED 0 (DISABLE)P0INT 0 (DISABLE)P1INT 0RESERVED

I2C=DISABLE, SYS=RESERVED, FLASHREG=DISABLED, FLASHARRAY=DISABLED, IOCON=DISABLE, SSP1=DISABLE, GPIO=DISABLE, WDT=DISABLE, CT32B0=DISABLE, CT16B1=DISABLE, PINT=DISABLE, ADC=DISABLE, CT32B1=DISABLE, DAC=DISABLE, CT16B0=DISABLE, UART=DISABLE, RAM=DISABLE, ROM=DISABLE, ACOMP=DISABLE, P1INT=DISABLE, SSP0=DISABLE, P0INT=DISABLE

Description

System clock control

Fields

SYS

Enables the clock for the AHB, the APB bridge, the Cortex-M0 FCLK and HCLK, SysCon, and the PMU. This bit is read only and always reads as 1.

0 (RESERVED): Reserved

1 (ENABLE): Enable

ROM

Enables clock for ROM.

0 (DISABLE): Disable

1 (ENABLE): Enable

RAM

Enables clock for RAM.

0 (DISABLE): Disable

1 (ENABLE): Enable

FLASHREG

Enables clock for flash/EEPROM register interface.

0 (DISABLED): Disabled

1 (ENABLED): Enabled

FLASHARRAY

Enables clock for flash/EEPROM array access.

0 (DISABLED): Disabled

1 (ENABLED): Enabled

I2C

Enables clock for I2C.

0 (DISABLE): Disable

1 (ENABLE): Enable

GPIO

Enables clock for GPIO.

0 (DISABLE): Disable

1 (ENABLE): Enable

CT16B0

Enables clock for 16-bit counter/timer 0.

0 (DISABLE): Disable

1 (ENABLE): Enable

CT16B1

Enables clock for 16-bit counter/timer 1.

0 (DISABLE): Disable

1 (ENABLE): Enable

CT32B0

Enables clock for 32-bit counter/timer 0.

0 (DISABLE): Disable

1 (ENABLE): Enable

CT32B1

Enables clock for 32-bit counter/timer 1.

0 (DISABLE): Disable

1 (ENABLE): Enable

SSP0

Enables clock for SSP0.

0 (DISABLE): Disable

1 (ENABLE): Enable

UART

Enables clock for UART. Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled.

0 (DISABLE): Disable

1 (ENABLE): Enable

ADC

Enables clock for ADC.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

WDT

Enables clock for WDT.

0 (DISABLE): Disable

1 (ENABLE): Enable

IOCON

Enables clock for I/O configuration block.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

SSP1

Enables clock for SSP1.

0 (DISABLE): Disable

1 (ENABLE): Enable

PINT

GPIO Pin interrupts

0 (DISABLE): Disable

1 (ENABLE): Enable

ACOMP

Enables clock for ACOMP.

0 (DISABLE): Disable

1 (ENABLE): Enable

DAC

Enables clock for DAC.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

P0INT

GPIO Port 0 interrupt

0 (DISABLE): Disable

1 (ENABLE): Enable

P1INT

GPIO Port 1interrupt

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

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